1. Field of the Invention
The present invention relates to a constant current circuit. More particularly, the present invention relates to a constant current circuit for preventing latch up generated at a constant current circuit in a PLL synthesizer IC used in a terminal equipment of a wireless telephone.
2. Description of the Prior Art
In order to meet the demand of recent miniaturization of telephone terminal equipment, it is also attempted to miniaturize the semiconductor integrated circuit (IC) built in the telephone terminal equipment. As a result, narrower separation areas between the elements bring about a newly-arising problem of a parasitic thyristor which is formed in an area between the elements and a separation layer, which has not been a serious problem until now. If high voltage generated by, for example, thunder raises the power supply potential Vcc momentarily, this parasitic thyristor in the constant current circuit shorts the IC circuit, which leads to a serious problem.
FIG. 9 shows a location of the constant current circuit built in PLL used for the telephone terminal equipment, for instance. In FIG. 9, the constant current circuit is used in PLL synthesizer IC for supplying current for a charge pump circuit, a phase-comparison circuit, a prescaler circuit and so on.
FIG. 7 shows a conventional constant current circuit. In FIG. 7, the constant current circuit has a capacitor X for preventing oscillation. This capacitor X is connected between a collector electrode an emitter electrode of a transistor Q1. An area 10 circumscribed by a chain line shows a part of an IC circuit including a base, an emitter, a collector of an oscillation transistor Q4 and the capacitor X of the constant current circuit. An area 12 circumscribed by a two-dot chain line shows a parasitic thyristor which is assumed to be formed between a point "a" and a point "d" in the area 10. This parasitic thyristor comprises a PNP parasitic transistor q1 and a NPN parasitic transistor q2. In the parasitic thyristor circuit 12, a resistor r1 is connected between an emitter of the transistor q1 and the point a which is connected to the voltage source Vcc via resistor R2, a resistor r2 is connected between a base of transistor q1 and the point a, a resistor r3 is connected between a base of the transistor q1 and the collector of transistor q1, a resistor r4 is connected between the base of transistor q2 and the point d, and a collector of the transistor q2 is connected to the point d which is connected the ground.
FIG. 8 shows an enlarged view of the thyristor elements actually formed on the IC. The thyristor elements are depicted in FIG. 7 as shown circumscribed by a two-dot chain line. In FIG. 8, a first N.sup.- well area is defined at a plane of substrate (P-sub). In the first N.sup.- well area, an N.sup.+ area for base contact, a P.sup.+ area for emitter contact, and a P.sup.+ area for collector contact are defined. On the other hand, a second N.sup.- well area is defined adjacent to the first N.sup.- well area in the substrate P-sub. Then a dielectric layer is formed on the second N.sup.- well area and then an electrode is formed on the dielectric layer to make the capacitor X.
The emitter electrode of the transistor Q4 is connected to the power supply potential node through a resistor R2, while both the base electrode and the collector electrode are connected to one of electrodes (conductive layer) of the capacitor X formed on the dielectric layer. The other electrode of capacitor X on the second N.sup.- well area is connected to a ground potential node via N area which is formed in the N.sup.- well area. As described above, the constant current circuit is formed on the IC using lateral type of transistors.
FIG. 8 shows only the base, the emitter, the collector and the capacitor X, and the other parts are omitted for simplicity of explanation. In such a construction, when the P-sub separation layer between the first N.sup.- well area and the second N.sup.- well area becomes narrower by miniaturizing the size of IC, a parasitic thyristor comprised of a PNP parasitic transistor q1 and a NPN parasitic transistor q2 are formed through nodes a, b, c and d in the first N.sup.- well area and the second N.sup.- well area in IC. This parasitic thyristor is depicted by the two-dot chain line in FIG. 7 between a power supply potential node and a ground potential node via the resistor R2. In other words, a parasitic thyristor circuit 12 is formed in addition to the usual IC circuit comprised of transistors Q4 and Q1 as shown in FIG. 8.
To explain this parasitic thyristor in detail, a parasitic resistor r1 is connected between an emitter of the parasitic transistor q1 and the emitter layer P.sup.+ of transistor Q4 (point a) which is connected to the power supply potential node via the resistor R2. A parasitic resistor r2 is connected between a base of the parasitic transistor q1 and the emitter layer P.sup.+ of transistor Q4 (point a). Furthermore, a parasitic resistor r3 is connected between a collector and the base of the parasitic transistor q1. The collector and the base of the parasitic transistor q1 are connected to the base and the collector of the parasitic transistor q2, respectively. A parasitic resistor r4 is connected between a base of the parasitic transistor q2 and the ground potential node. An emitter of the parasitic transistor q2 is grounded directly via the point d and the N layer in the N.sup.- well area.
An operation of the parasitic thyristor is explained below. If the power supply potential Vcc rises momentarily, for example, due to high voltage generated by thunder, this high voltage is applied to the emitter (point a) of the transistor Q4 via the resistor R2, and a current i.sub.1 flows from the point a to the ground (point d) via the parasitic resistor r2, parasitic resistor r3, parasitic resistor r4. If the value of the current i.sub.1 is large enough to generate a voltage drop through the resistor r2 which is greater than the voltage of the base-emitter voltage V.sub.BE (about 0.7 V) of the parasitic transistor q1, and also if the voltage drop through the resistor r4 becomes grater than the voltage of the base-emitter voltage V.sub.BE (about 0.7 V) of the parasitic transistor q2, both parasitic transistors q1 and q2 are operated in the ON state. Therefore, the voltage node potential Vcc is shorted 2 to the ground through the parasitic thyristor.
As explained above, in the prior constant current circuit, when a high voltage is applied to the power source potential node by some reasons, the power source potential node is shorted to the ground which makes a serious problem to the constant current circuit.
It is an object of the present invention to provide a constant current circuit having a latch-up prevention measures for preventing the operation of the parasitic thyristor even if the high voltage is applied to the power source potential node.